system verilog unpacked array assignment

SystemVerilog Unpacked Arrays

An unpacked array is used to refer to dimensions declared after the variable name.

Unpacked arrays may be fixed-size arrays, dynamic arrays , associative arrays or queues .

Single Dimensional Unpacked Array

Multidimensional unpacked array, packed + unpacked array.

The example shown below illustrates a multidimensional packed + unpacked array.

In a multidimensional declaration, the dimensions declared before the name vary more faster than the dimensions following the name.

An Introduction to SystemVerilog Arrays

This post of the the first of two which talk about SystemVerilog arrays . In this post, we will talk about static arrays , array assignment , loops and packed vs unpacked arrays .

In SystemVerilog, we can write arrays which have either a fixed number of elements or a variable number of elements.

Fixed size arrays are also known as static arrays in SystemVerilog. When we declare a static array, a fixed amount of memory is allocated to the array at compile time . As a result of this, we can't add new elements or resize the array during simulation.

In contrast, we can allocate extra memory or resize a dynamic array while a simulation is running.

Static arrays are generally simpler to use than dynamic arrays and are similar to verilog arrays . Therefore, we will discuss static arrays in more depth in the rest of this post.

In the next post in this series, we will talk about more advanced SystemVerilog arrays. This includes a discussion of dynamic arrays , queues and associative arrays .

Static Arrays in SystemVerilog

Static arrays are the simplest form of array to work with in SystemVerilog. We use static arrays in exactly the same way as we would use an array in verilog .

The code snippet below shows the general syntax which we use to declare a static array in SystemVerilog.

In this construct, we use the <elements> field to declare how many elements are in our array.

In contrast to verilog, we can use a single number in the <elements> field to determine how many elements are in the array.

When we use this approach, SystemVerilog creates a zero indexed array as this is the most commonly used type of array. This approach is also consistent with the way that arrays in C are declared and created.

However, we can also use the old verilog syntax to specify a value for the low and high indexes in our array. When we use this approach, the <elements> field takes the form [high_index : low_index].

We previously discussed the rest of the fields used in this declaration in the post on SystemVerilog Data Types .

To show how we would declare a SystemVerilog array using both approaches, let's consider a simple example. In this example, we will create an array of 4 bit logic types and we want to have a total of 16 elements.

The SystemVerilog code below shows the two different methods we could use to create this array.

• Array Assignment and Literals

After we have created an array in our SystemVerilog code, we can access individual elements in the array using square brackets.

For example, if we wanted to assign some data to the first element in an array then we would use the syntax shown in the code snippet below.

We use this same syntax to access array elements in verilog.

However, we can also use array literals to assignment data to arrays in SystemVerilog. Array literals provide us with a quick and convenient method to assign values to multiple elements in the array at the same time.

The code snippet below shows the general syntax we use to assign data to an array using an array literal.

We use the <values> field in the above code snippet to assign a value to every element in the array.

We can use three different methods to assign data to the <values> field in this construct. The most common method is to use a comma separated list of values.

The SystemVerilog code below shows how we would assign elements to an array using this technique. We can also simulate this code on eda playground .

In addition to this method, we can also use other techniques to assign the same value to multiple elements in the array.

We actually have two methods which we can use for this. Both of these methods are more concise than writing a comma separated list with duplicated values.

The first approach is to use another pair of curly braces inside the list which shows the value we want to assign. We can then put a number in front of the braces to indicate how many consecutive elements should be assigned this value.

As an example, we might want to create an array and assign all of the elements to 0. The code snippet below shows how we would do this using array literals. This code can also be simulated on eda playground .

In addition to this, we can also use the SystemVerilog default keyword inside our array literal.

We more typically use the default keyword inside of SystemVerilog struct types which we will talk about in a future post.

However, we can also use the default keyword as a convenient way to assign the same value to every element in a static array. We can't use this technique with dynamic arrays though.

As an example, we might want to create an array and assign all of the elements to 0. The code snippet below shows how we would do this using the default keyword. We can also simulate this code on eda playground .

When we work with arrays in SystemVerilog it is possible that we may try to assign data to an array element which is out of bounds . When we are working with static arrays, any attempt to do this is simply ignored.

Array Loops

When we work with arrays in any programming language, one common operation is iterating over every element in the array.

There are actually two different methods which we can use to do this in SystemVerilog.

In both case, we make use of a SystemVerilog loops . There are several types of loop which we can use in SystemVerilog and we discuss this in more detail in a later post.

However, let's take a look at both of the methods we can use to iterate over an array in more detail.

• The for loop

The first method makes use of the SystemVerilog for loop which we discuss in more depth in a later post.

The code snippet below shows the general syntax which we use to implement a for loop in SystemVerilog. This syntax is exactly the same as we use in verilog for loops .

We use the <initial_condition> field to set the initial value of our loop variable .

The <stop_condition> field is a conditional statement which determines how many times the loop runs. The for loop will continue to execute until this field evaluates as false.

The <increment> field determines how the loop variable is updated in every iteration of the loop.

We can use the for loop to generate the index for every element in an array. We can then use the loop variable to access each of the elements in the array in turn.

The code snippet below shows how we would do this in SystemVerilog. This example can also be simulated on eda playground .

In this example, we initialize the loop variable (i) to 0 in order to get the lower index of the array. We then use the $size macro to get the index of the final element in our array.

The $size macro is a built in function in SystemVerilog which returns the number of elements in an array.

Finally, we use the SystemVerilog increment operator to increment the value of the loop variable by one on every iteration. As we can see for this example, we can use C style increment and decrement operators in our SystemVerilog code.

From this we can see how the loop variable i is increased fro 0 to 7 in the for loop. This allows us to access each of the array elements in turn by using the loop variable as an index.

• The foreach Loop

The second method which we can use to loop over an array in SystemVerilog is the foreach loop.

This is a new type of loop which was introduced as a part of the SystemVerilog language. The foreach loop is designed to provide a more concise way of looping over an array.

The code snippet below shows the general syntax for the foreach loop.

In this construct, we use the <array_name> field is select the array which we want to loop over.

The <iterator> field is then automatically incremented from the low index to the high index of the selected array.

We can use the <iterator> field in the body of our foreach loop in the same way as we used the loop variable in the body of the for loop.

As we can see, we don't need to manage the array index when we use the foreach loop. As a result of this, we generally find that the foreach loop is easier to use than the for loop.

To demonstrate how we would use the foreach loop, let's rewrite the example from the section on for loops.

In this example, we created an array of 8 elements and then looped over each element in turn.

The code snippet below shows how we would implement this functionality with a foreach loop. We can also simulate this example on eda playground .

As we can see from this example, when we use a foreach loop we generally have to write less code to achieve the same result.

Multi Dimensional Arrays in SystemVerilog

So far, all of the arrays which we have discussed in this post have been one dimensional.

However, we can also create SystemVerilog arrays which have more than dimension. To do this, we simply add another field to the end of the array declaration.

The code snippet below shows the general syntax we would use to create a 2D array in SystemVerilog.

Both of the <elements> fields in this construct take the same form as the <element> field which we previously discussed in the section on static arrays.

As a result, we can either use a single number to determine the number of elements or we can specify a value for the low and high indexes. When we use the second approach, the <elements> field takes the form [high_index : low_index].

We can add as many <element> fields as needed to create a multidimensional array. For example, if we need a 3D array, then we would use a total of 3 <element> fields in our declaration.

In order to better demonstrate how we use multidimensional arrays in SystemVerilog, let's consider a basic example.

For this example, let's say that we want to create an array which has 2 elements both of which contain 4 8-bit wide logic types.

To do this, we simply need to add an extra field to the end of our normal array declaration. The code snippet below shows how we would do this.

• Assigning Data to Multidimensional Arrays

We use the same method to assign a multidimensional array as we would for a 1D array. However, we now use a pair of square brackets to define the element in both dimensions of the array.

As an example, suppose we want to assign the value of AAh to the the last element in both dimensions of the example array we declared in the previous section. The SystemVerilog code below shows how we would do this.

We can also use arrays literals to assign data to multidimensional arrays in SystemVerilog.

However, we now have to create a literal which itself contains a separate array literal for each dimension of the array.

For example, if we have a 2D array then we would create an array literal which is made up of 2 further array literals.

As an example, let's consider the case where we want to populate both elements of the 2D array example we created in the previous section.

However, we want all elements of the first dimension to be set to 0xFF and all elements in the second dimension to be set to 0.

The code snippet below shows how we would create an array literal to populate the entire 2D array with the required data. This code can also be simulated on eda playground .

• Packed and Unpacked Arrays in SystemVerilog

In all of the examples which we have considered so far, we have used unpacked arrays.

This means that each of the elements in the array is stored in a different memory location during simulation.

For example, suppose we have an array which consists of 4 8-bit elements. The code snippet below shows how we would create this is SystemVerilog.

As most simulators use 32 bit wide memory locations, we would end up with the memory contents shown below during simulation.

As we can see from this example, unpacked arrays can result in inefficient usage of memory as parts of the memory are unused.

In SystemVerilog, we can also use packed arrays to store our data in. Packed arrays will result in more efficient usage of memory when we run our simulations in some instances.

In contrast to unpacked arrays, all elements of a packed array are stored continuously in memory. This means that more than one element can be stored in a single memory location.

The code snippet below shows the general sytnax we use to declare a packed array in SystemVerilog.

All of the fields in the packed array declaration are the same as in the unpacked declaration. In fact, the only difference is that the <elements> field now comes before the <variable_name> field rather than after it.

To demonstrate how packed arrays are different to unpacked arrays, let's consider a simple example.

For this example, we will again create an array of 4 8-bit elements. However, this time we will declare the array as a packed type array.

The SystemVerilog code below shows would we declare this packed array.

This example would result in the memory allocation shown below.

We can see from this that the packed array has used a single 32-bit wide memory location to store the entire contents of the array.

In comparison to the unpacked array example, we can see how the packed array uses less memory by packing all of the data into a single memory location in this instance.

What is the difference between static arrays and dynamic arrays in SystemVerilog?

Static arrays have a fixed number of elements which are determined at compile time. In contrast, dynamic arrays don't have a fixed sized and we can add or remove elements during simulation.

Write the code to create an array which consists of 4 8-bit elements. Use an array literal to assign all of the elements in the array to 0.

Write a foreach loop for the array which you created in the last exercise

Write the code to declare a 2D array of int types. The array should have 2 elements in the first dimension and 8 elements in the second dimension.

What is the difference between an unpacked array and a packed array?

Each element of an unpacked array is stored in an individual memory address. In contrast, packed arrays are stored continuously in memory meaning that several elements can be stored in a single memory address.

2 comments on “An Introduction to SystemVerilog Arrays”

logic [7:0] [3:0] example; will give 8 nibbles

I think you need logic [3:0] [7:0] example; for your example

Thanks for pointing out the typo, I have now corrected it.

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Verification Guide

Packed and Unpacked array

Packed and unpacked array in systemverilog.

Table of Contents

• The term packed array is used to refer to the dimensions declared before the data identifier name
• The term unpacked array is used to refer to the dimensions declared after the data identifier name

Packed array

• Packed arrays can be of single bit data types (reg, logic, bit), enumerated types, and recursively packed arrays and packed structures
• Vector: A vector is a multi-bit data object of reg/logic/bit declared by specifying a range
• Scalar: Scalar is 1-bit data object of reg/logic/bit declared without specifying a range
• A packed array is a mechanism for subdividing a vector into sub-fields, which can be conveniently accessed as array elements.
• A packed array is guaranteed to be represented as a contiguous set of bits.

Packed array example

The below diagram shows storing packed array as a  contiguous set of bits.

UnPacked array

• Unpacked arrays can be of any data type.
• Unpacked arrays shall be declared by specifying the element ranges after the identifier name.
• An unpacked array may or may not be so represented as a  contiguous set of bits.

Unpacked array example

Below diagram shows storing unpacked array as a  non-contiguous set of bits.

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SystemVerilog Arrays

An array is a group of variables having the same data type. It can be accessed using an index value. 

An index is a memory address and the array value is stored at that address.

Types of an array

Fixed-size array in systemverilog, single dimensional array.

• Multidimensional array a. Two-dimensional array. b. Three-dimensional array
• Packed and Unpacked array in SystemVerilog
• Dynamic array in SystemVerilog
• Associative array in SystemVerilog

Array size is fixed throughout the simulation. Its value will be initialized with a ‘0’ value.

Array assignment

Multidimensional array.

A multidimensional array is also known as an array of an array. In mathematics, we studied matrix, this can be understood as a multidimensional matrix.

Two-dimensional array

Three-dimensional array

Scalar vs vector.

The data object which does not have a specific range for bit/logic/reg is a scalar.

The data object which has a specific range for bit/logic/reg is a vector.

Packed and Unpacked array

Packed array.

A packed array refers to the dimension mentioned before the variable or object name. This is also known as the vector width .

Memory allocation is always a continuous set of information that is accessed by an array index.

Unpacked array

An unpacked array refers to the dimension mentioned after the variable or object name.

Memory allocation may or may not be a continuous set of information.

Combination of a packed and unpacked array

All arrays mentioned above are types of static arrays .

System Verilog Tutorials

Verilog Pro

SystemVerilog Arrays, Flexible and Synthesizable

In my last article on plain old Verilog Arrays , I discussed their very limited feature set. In comparison, SystemVerilog arrays have greatly expanded capabilities both for writing synthesizable RTL, and for writing non-synthesizable test benches. In this article, we’ll take a look at the synthesizable features of SystemVerilog Arrays we can use when writing design RTL.

Packed vs Unpacked SystemVerilog Arrays

Verilog had only one type of array. SystemVerilog arrays can be either packed or unpacked . Packed array refers to dimensions declared after the type and before the data identifier name. Unpacked array refers to the dimensions declared after the data identifier name.

Packed Arrays

A one-dimensional packed array is also called a vector. Packed array divides a vector into subfields, which can be accessed as array elements. A packed array is guaranteed to be represented as a contiguous set of bits in simulation and synthesis.

Packed arrays can be made of only the single bit data types ( bit , logic , reg ), enumerated types, and other packed arrays and packed structures. This also means you cannot have packed arrays of integer types with predefined widths (e.g. a packed array of byte ).

Unpacked arrays

Unpacked arrays can be made of any data type. Each fixed-size dimension is represented by an address range, such as [0:1023], or a single positive number to specify the size of a fixed-size unpacked array, such as [1024]. The notation [size] is equivalent to [0:size-1].

Indexing and Slicing SystemVerilog Arrays

Verilog arrays could only be accessed one element at a time. In SystemVerilog arrays, you can also select one or more contiguous elements of an array. This is called a slice . An array slice can only apply to one dimension; other dimensions must have single index values in an expression.

Multidimensional Arrays

Multidimensional arrays can be declared with both packed and unpacked dimensions. Creating a multidimensional packed array is analogous to slicing up a continuous vector into multiple dimensions.

When an array has multiple dimensions that can be logically grouped, it is a good idea to use typedef to define the multidimensional array in stages to enhance readability. But notice the order of the dimensions become a little confusing.

SystemVerilog Array Operations

SystemVerilog arrays support many more operations than their traditional Verilog counterparts.

+: and -: Notation

When accessing a range of indices (a slice ) of a SystemVerilog array, you can specify a variable slice by using the [start+:increment width] and [start-:decrement width] notations. They are simpler than needing to calculate the exact start and end indices when selecting a variable slice. The increment/decrement width must be a constant.

Assignments, Copying, and other Operations

SystemVerilog arrays support many more operations than Verilog arrays. The following operations can be performed on both packed and unpacked arrays.

Packed Array Assignment

A SystemVerilog packed array can be assigned at once like a multi-bit vector, or also as an individual element or slice, and more.

Unpacked Array Assignment

All or multiple elements of a SystemVerilog unpacked array can be assigned at once to a list of values. The list can contain values for individual array elements, or a default value for the entire array.

This article described the two new types of SystemVerilog arrays— packed and unpacked —as well as the many new features that can be used to manipulate SystemVerilog arrays. The features described in this article are all synthesizable, so you can safely use them in SystemVerilog based RTL designs to simplify coding. In the next part of the SystemVerilog arrays article, I will discuss more usages of SystemVerilog arrays that can make your SystemVerilog design code even more efficient. Stay tuned!

• Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification
• 1888-2012 IEEE Standard for SystemVerilog
• SystemVerilog for Design Second Edition: A Guide to Using SystemVerilog for Hardware Design and Modeling

Sample Source Code

The accompany source code for this article is a toy example module and testbench that illustrates SystemVerilog array capabilities, including using an array as a port, assigning multi-dimensional arrays, and assigning slices of arrays. Download and run it to see how it works!

[lab_subscriber_download_form download_id=11].

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36 thoughts on “SystemVerilog Arrays, Flexible and Synthesizable”

Really nice article Jason. Makes for a great quick introduction and reference. I have personally found System Verilog arrays as one of the best ways to convert a Verilog user to System Verilog.

Chapter 5 and specifically Fig 5-5 in the System Verilog for Design book are the best: http://read.pudn.com/downloads166/sourcecode/math/758655/Springer%20-%20SystemVerilog%20for%20Design,%202nd%20Edition.pdf

I believe you have a mistake at the article. Regarding: busB = busA[7:6]; // select a 2-vector slice from busA busB = busA[6+:1]; // equivalent to busA[7:6]

but, busA[6+:1] is different from busA[7:6]! busA[6+:1] is actually busA[6:6] and: busA[6+:2] is busA[7:6]

Regards, Tomer

Hi Tomer. Yes you’re correct! I made a typo there, it’s fixed now. Thanks for spotting it!

I don’t see why we need packed/unpacked array for synthesis. FPGA is not limited with a fix size of memory like computer. The compiler should keep only what we need. Compiler will never allocate useless bits, it’s even opposite.

Same for packed and unpacked struct. What is the purpose if not only simulation speed?

Hi Alexis. If your question is why the packed versions are needed, with traditional synthesis tools you need packed arrays/structs/unions to tell the synthesis tool exactly how many bits and how you want to pack a datastructure. FPGA actually does have limited resources, and each additional (unnecessary) bit of a calculation takes up an additional lookup table. Similarly an extra bit in a calculation will require more gates in an ASIC. I wonder if part of the reason came from this desire for hardware engineers to have complete low level control of the synthesis result.

However, I think generally synthesis tools and Verilog/SystemVerilog rules are smart enough to figure out the minimum number of bits you want in a calculation. So you could argue since tools are so smart, why do we still need to specify the packing. I don’t have a good answer, but I think one day (maybe soon) you will be right and we won’t need to specify packed structures anymore.

I see, exactly since the synthesis tools removes the unused bits from the RTL. Then even if I set unpacked array, at the end, the RTL will be as if I chose packed array. Thank you and sorry for my late reply.

Hi May I confirm if there is a typo on this example typedef bit [4:0] bsix; // multiple packed dimensions with typedef bsix [9:0] v5; // equivalent to bit[4:0][9:0] v5

typedef bsix mem_type [0:3]; // array of four unpacked ‘bsix’ elements mem_type ba [0:7]; // array of eight unpacked ‘mem_type’ elements // equivalent to bit[4:0][9:0] ba [0:3][0:7]

Should the last comment be bit[4:0] ba [0:3][0:7] instead of bit[4:0][9:0] ba [0:3][0:7]?

Yes you’re right! Thanks for catching it!

Got it, thanks. By the way, if I have a 3D array, and I want to be able to slice of a 2D portion when accessing it, would you recommend to build a 3D array as “logic [HEIGHT-1:0][WIDTH-1:0] array [DEPTH]” or “logic [WIDTH-1:0] array [DEPTH][HEIGHT]”

For example, I have several submodules that expect a 2D array input, and I plan to connect them by slicing off the 3D array, so just wondering which way is preferred, “logic [HEIGHT-1:0][WIDTH-1:0] array [DEPTH]” or “logic [WIDTH-1:0] array [DEPTH][HEIGHT]”

You can slice a 2D array out of a 3D array with both ways of coding, or even “logic array [width][depth][height]”. The difference is whether you want the 2nd (middle) dimension to be packed (left of array name) or unpacked (right of array name). In your example, since each “element” is only a single bit (logic), it probably doesn’t matter which way you code it; I would actually probably code it as “logic array [width][depth][height]” to clearly show each element is only a single bit. But if you really meant a 2D array of multi-bit vector, then I would use “logic [vector_width-1:0] array [depth][height]” to show that more clearly.

The packed vs unpacked dimensions matter more if you are instead creating multi-dimensional arrays of structs or more complex data types, in which case there may be rules that the data structures must be packed (on the left) for synthesis.

Got it, thanks for sharing 🙂

1- Why do we still need to use [7:0]? We can use `busB = busA[0+:8];` and use directly the number of bits. It avoids using paraneter like `bus[PARAM-1:0]`, better to write `bus[0+=PARAM]`

2- You said `bus[6+:2]` is equivalent to `bus[7:6]` how to use big endianness to get bus[6:7]? I guess it’s not possible.

Sorry, I misread and I simulated. We can’t define logic using +:, you can delete the question.

Hi, I am writing a code in system verilog, and I wondered if there is a way to index an array from 1? Is this correct, and can I access array a from 1 to q_size?

logic a [1:q_size];

Also, unrelated question but I would be glad if you could give me an answer: I generate a queue made of number (q_size) of my blocks, which are connected with signals, so I need a number (q_size) of signals, which I intenteded to define as example above. In generate for loop I map signals to ports this way:

my_module( .my_input(a[i+1]) //i is genvar )

Is this correct, can I work with indexes this way? Thank you VERY MUCH 🙂

Hi Ivana. It is certainly possible to index an array from 1, like what you wrote. Hardware designers generally like to think and code with index starting with 0 for convenience (for example in your code you wouldn’t need a +1 if the index started at 0). Yes you can use a genvar to index into a vector. Your code should work.

Thanks for the awesome blog posts. Arrays with negative indices seem to compile (at least using the Cadence tools). What I am wondering is, do arrays with negative indices actually synthesize?

parameter integer unsigned width = 0; logic [width-1:0] x;

This compile and in SimVision I actually see x[-1:0] in waves. I am curious to know if this is a quirk in the simulator or does this actually synthesize to a two bit logic equivalent?

Thanks, Sami

Hi Sami. Another interesting question 🙂 I have never used a negative index because that goes against the coding guidelines at work, so I don’t know for sure… but I would guess it would work as expected (if your synthesis tool doesn’t complain).

I have a question about the comparison of mixed arrays that I think would fit in here:

consider the following code:

module testModule #( parameter logic [7:0] TP_A = 8’h01, parameter logic [7:0] TP_B = 8’h02, parameter logic [7:0] TP_C = 8’h03, parameter logic [7:0] TP_D = 8’h04 )( input logic clock_104, input logic reset_n, input logic [7:0] sampleData [12:0] output logic [7:0] errorCnt );

logic [7:0] comp0 [12:0]; assign comp0 = ‘{TP_A,TP_B,TP_C,TP_D,TP_A,TP_B,TP_C,TP_D,TP_A,TP_B,TP_A,TP_B,TP_C};

always @(posedge clock_104) begin if (reset_n == 1’b0) errorCnt <= '{default:0}; else begin if (sampleData == {TP_A,TP_B,TP_C,TP_D,TP_A,TP_B,TP_C,TP_D,TP_A,TP_B,TP_A,TP_B,TP_C} ) begin // this generates an error of illegal comparison to unpacked array if (sampleData == comp0 ) begin // this works fine

Why does one if statement work fine and the other one creates an error? Are they not doing the same thing?

Thank you for your help!

Hi Tom. I tried some variations of your experiment.

A pure array literal. This worked. if (sampleData == ‘{8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00, 8’h00}

Add an apostrophe in front of the array: if (sampleData == ‘{TP_A,TP_B,TP_C,TP_D,TP_A,TP_B,TP_C,TP_D,TP_A,TP_B,TP_A,TP_B,TP_C} )

The simulator (VCS 2014.10) then reported the following error:

Error-[SV-IUAP] Illegal use of assignment pattern design.sv, 22 “(sampleData == ‘{TP_A, TP_B, TP_C, TP_D, TP_A, TP_B, TP_C, TP_D, TP_A, TP_B, TP_A, TP_B, TP_C})” An assignment pattern can only be used in one of the sides of an assignment-like context. Please consider rewriting it using individual array elements.

I suspect the simulator is somehow trying to do two levels of assignments in the error case, and that cannot be done within a comparison? However, I couldn’t find a statement in the LRM that explained why it is not allowed either…

That is a kind of weird. Thank you for taking the time and looking into this. I appreciate it.

is input node [6-1:0] A the same same input node [5:0] A

Hi Mike. Yes that is identical.

Hi Jason, Thank you for the wonderful forum. I have a few queries. How can I check the bit order ( MSB first and LSB last) of a packed array? e.g. input logic[7:0] test1; and output logic [7:0] out1; Would be kind to explain me.

There are several SystemVerilog system tasks that you can use to do that. See section 20.7 Array Querying Functions of the 2012 SystemVerilog LRM. Some examples are:

• $left shall return the left bound of the dimension. For a packed dimension, this is the index of the most significant element. For a queue or dynamic array dimension, $left shall return 0.
• $right shall return the right bound of the dimension. For a packed dimension, this is the index of the least significant element. For a queue or dynamic array dimension whose current size is zero, $right shall return –1.
• For a fixed-size dimension, $increment shall return 1 if $left is greater than or equal to $right and –1 if $left is less than $right. For a queue or dynamic array dimension, $increment shall return –1.
• $low shall return the same value as $left if $increment returns –1, and the same value as $right if $increment returns 1.
• $high shall return the same value as $right if $increment returns –1, and the same value as $left if $increment returns 1.
• $size shall return the number of elements in the dimension, which is equivalent to: $high – $low + 1.

Thank you Jason for your venerated inputs.

I’d like to try this, but not having much luck.. for example, I’ve created an .sv module that declares eight, 16-bit registers:

module test ( output reg [ 15 : 0 ] regTest[ 0 : 7 ] … );

Then in another .sv file, I try to instantiate like this:

wire [15:0]test[0:7]; test test_u0 ( .regTest (test) … );

However the above says an error that it cannot bind.. I’ve tried using the packed syntax, but it doesn’t seem to make any difference.. any suggestion what might be the problem?

Thanks! Ben

Hi Ben. I tried your code out on edaplayground here , and didn’t have any problem. Perhaps something else was causing the issue?

Hi want to extract only columns in packed 2-D array, for eg logic [255:0][299:0] array1 has 256 rows each having 300 bits ; if I wanted to extract 1st column through array slicing operation how do I do it? Like array1[0] gives first row array1[1] gives second row etc ; Thanks a lot

Hi Venkat. The array definition makes extracting one dimension easier than the other, so you should be careful about how you define the array. To accomplish what you want to do, you can write a loop to extract each element that you need and assign that element to a new 256-entry single dimensional array.

Can I include an unpacked array in a struct or an interface? For example, I like to pass an FIFO and some other info of a module to another to snooping. can I have a struct like this: typedef struct packed { logic [5:0] dev_sel; logic [31:0] wr_pending_fifo_dv; logic [31:0] wr_pending_fifo_mem [128]; } dev_wr_fifo_s;

Would an interface have the same elements?

Thanks Agnes

Hi Agnes. If you create an unpacked struct (typedef struct, without the packed keyword), then you can have an unpacked array like the wr_pending_fifo_mem in the structure. However, Design Compiler will not synthesize an unpacked struct. What are you trying to achieve? Putting a FIFO into a struct seems to be a bit of a strange construct.

Always thanks to your post. Again, I hope to ask clarify below comment. /////////////////////////////////////////////////////////////////////////// bit [3:0] [7:0] joe [0:9] // 10 elements of 4 8-bit bytes // (each element packed into 32 bits) typedef bit [4:0] bsix; // multiple packed dimensions with typedef bsix [9:0] v5; // equivalent to bit[4:0][9:0] v5 typedef bsix mem_type [0:3]; // array of four unpacked ‘bsix’ elements mem_type ba [0:7]; // array of eight unpacked ‘mem_type’ elements // equivalent to bit[4:0] ba [0:3][0:7] – thanks Dennis! /////////////////////////////////////////////////////////////////////////// Considering its semantic, I think it needs to be fixed as below. In my previous experience, I was also confused for that. 1. equivalent to bit[4:0][9:0] v5 => equivalent to bit[9:0][4:0] v5 2. equivalent to bit[4:0] ba [0:3][0:7] => equivalent to bit[4:0] ba [0:7][0:3]

Hi Yunsung. I just ran a test to prove it to myself. You’re right! Thanks for correcting this major mistake!

Is accessing to array slices with dynamic indexing but fixed width synthesizable? For example:

// input_byte is a 8 bit logic input // input_index is 3 bit logic input localparam int unsigned FIXED_WIDTH = 8; logic[63:0] data_array; data_array[input_index *FIXED_WIDTH +: FIXED_WIDTH] <= input_byte;

Hi Veli. I think that should be synthesizable. I have written similar code where the LHS is a dynamic index to an array. I have not additionally used a fixed width slice, but I think since the width is a fixed parameter, it shouldn’t be a problem. A dynamic index and a dynamic width, I think would be a problem.

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SystemVerilog中的Packed和Unpacked数组

unpacked数组和packed数组的主要区别是unpacked数组在物理存储时不能保证连续，而packed数组则能保证在物理上连续存储。

另一种看待unpacked数组和packed数组差异点的角度是，packed数组可以看成一个整体，一个单一向量。

unpacked数组的维度是在数组名称 之后 声明的，数组中内容可以是任何数据类型或者其他数组。

正如你所注意到的，uP0到uP3分散在多个word中，它们不是连续的。

packed数组的维度是在数组名称 之前 声明的,下面是一个packed数组的例子:

这个打包数组可以表示为如下所示:

正如上图所示的，p3到p0在物理空间上是连续的。

某种意义上，这个所谓的packed就是表示是否在物理空间连续存放。

2-D Packed Array

在上面的例子中，我们声明了一个名为“m_data”的二维packed数组。请注意,所有维度的声明都位于数组名称的左侧。

这个数组一共有4(行)，每行8bit(列)，总的大小是4*8 = 32bit。因为是packed数组，其中所有的bit都是连续存储的，所以可以按照bit单独索引到。

我们给这个数组赋值(32'h 0102_0304)，然后打印相应的4行数据。

3-D Packed Array

3维数组和2维数组类似。

在上面的例子中，我们声明了一个三维packed数组，命名为“m_data”，一共是3 2 8 = 48bit。由于这是一个packed数组，48bit在物理空间上是连续分配的。 我们可以理解为：

1-D Packed and1-D Unpacked Array

下面是一个一维packed数组和1维unpacked数组的示例:

在上面的例子中，我们声明了一个1维unpacked数组("v1",共包含8项)，数组中的每一个内容又是一个packed数组（bit [31:0]）“v1”。我们可以理解为一个深度为8，宽度为32的存储器。

4-D Unpacked Array

我们声明一个4维unpacked数组，所有维度相关的声明都在数组名称的右边

如果一个unpacked数据项使用1word存储，上面的数组就需要物理空间

1-D Packed and3-D Unpacked Array

上面这个示例，是一个4*3 * 2个unpacked数组，其中每一个数据项都是一个8bit的packed数组。

如果每一个unpacked数据项使用1word存储，那么数组uP总的存储空间就是

2-D Packed and2D-Unpacked Array

上面声明了一个2维unpacked 数组，每个数组项都是一个2维的packed数组。所以，如果每个unpacked数据项使用1word存储，那么总的存储空间是：

3-D Packed and1-D Unpacked Array

上面声明了一个1维unpacked数组uP，一共4项，每项是一个3维packed数组。如果每个unpacked数据项使用1word存储，那么总的存储空间是

因为1word装不下一个packed数组