concurrent signal assignment statement in vhdl

VHDL Concurrent Conditional Assignment

The Conditional Signal Assignment statement is concurrent because it is assigned in the concurrent section of the architecture. It is possible to implement the same code in a sequential version, as we will see next.

The conditional signal assignment statement is a process that assigns values to a signal.

It is a concurrent statement; this means that you must use it only in concurrent code sections.

The statement that performs the same operation in a sequential environment is the “ if ” statement.

The syntax for a conditional signal assignment statement is:

This is a simple example of a two-way mux as reported here:

The output “ a ” is equal to “ b ” when the selector “ c ” is “1” else is equal to “ d ”

Concurrent Conditional Signal Assignment Example 1

This example extends the previous one. This is a 4-way mux, implemented as concurrent code.

The architecture declarative section is empty. As you can notice, we don’t care about how the mux is implemented.

In this moment we don’t’ talk about logic gate, and or nand ect, we are describing the behavior of circuit using a high level description.

A graphical representation can be this one.

It is up to the synthesizer to implement the best architecture on the selected technology in terms of logic gates. In fact if you are using FPGA the synthesizer will use LUT to map the VHDL functions, if you are implementing an ASIC the synthesized logic will depend on differ technology and will be implemented using, for instance, NAND, OR, NOR gate, depending on the technology.

Running the RTL compiler on Altera Quartus II , this is the output of the RTL viewer, if we try to layout this mux4 .

As clear, the RTL translation is implemented in terms of AND gate and 2-way mux. The output “ e ” is generated by cascading 3 two-way mux.

This is the output of the Altera MAP viewer selecting Cyclone IV FPGA technology. Our mux4 is implemented using LOGIC_COMB_CELL Look Up Table present in the Cyclone IV FPGA . This example should clarify the meaning of “technology dependent”.

Concurrent Conditional Signal Assignment Example 2

This example is the same 4-way mux as the previous one, in which we used a different syntax to implement the selector. In this case, we have introduced the statement “with select”.

In the architecture declarative section, we declared a signal “ sel ” of type integer used to address the mux. The signal “ sel ” is coded as binary to integer.

The statement “ with select ” allows compacting the syntax of the mux code. Note the introduction of the “ other ” keyword. It is necessary because the mux assignment cover only 3 of the 2^32 possible integer values. If we try to layout the code, it is interesting to see how RTL viewer interprets the VHDL code:

This case is different from the previous one. We can notice that the VHDL relative to the signal sel is decoded in order to implement mux selection and that the output mux is implemented as 4-way mux. So the RTL view of the RTL code is totally different from the previous one.

The FPGA used in this example is the same as the previous example, in fact the output of Altera MAP viewer have the same implementation of the previous RTL code as clear if we make a comparison between the two implementations.

These two examples should clarify the meaning of behavioral. We have seen two different implementations of a simple mux mapped on the same hardware :

implementation of different RTL code can generate the same hardware logic.

Of course, gaining the sensibility to write good VHDL/RTL code is only a matter of time and experience . If you will follow the course, you will find good advices in order to gain all the shortcuts useful reduce this amount of time.

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How to create a concurrent statement in VHDL

A concurrent statement in VHDL is a signal assignment within the architecture, but outside of a normal process construct. The concurrent statement is also referred to as a concurrent assignment or concurrent process.

When you create a concurrent statement, you are actually creating a process with certain, clearly defined characteristics. Concurrent statements are always equivalent to a process using a sensitivity list, where all the signals to the right of the signal assignment operator are on the sensitivity list.

These shorthand notation processes are useful when you want to create simple logic which results in the assignment of a single signal. Instead of typing out a full process construct with sensitivity lists and all of that, you can simply assign to the target signal directly in the architecture.

This blog post is part of the Basic VHDL Tutorials series.

When used correctly, the intention of the code will still be pretty clear. No need to create a process for every single bit you want to flip.

In this video, we learn how to create a concurrent statement:

The final code we created in this tutorial:

The waveform window in ModelSim after we pressed run, and zoomed in on the timeline:

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We can see from the waveform that Mul1 , Mul2 , and Mul3 behave exactly the same. This is because the concurrent statement and the two processes we created are equivalent.

A concurrent statement works just like a process. All signals to the right of the <= are automatically added to the sensitivity list. This means that the signal to the left of the <= will be updated whenever one of the signals that are evaluated change.

There are many ways to multiply numbers in VHDL. In this exercise we multiplied the Uns signal by 4, using bit shifting. All our signals are of unsigned type, meaning that they are interpreted by numbers. Appending a 0 to the right of a binary number is the same as multiplying it by 2.

• A concurrent statement is a signal assignment directly in the architecture region
• Concurrent statements are equivalent to a process with all evaluated signals on the sensitivity list

Go to the next tutorial »

I’m from Norway, but I live in Bangkok, Thailand. Before I started VHDLwhiz, I worked as an FPGA engineer in the defense industry. I earned my master’s degree in informatics at the University of Oslo.

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vhdl_reference_93:concurrent_signal_assignment

Concurrent signal assignment ,... <= ..."

Concurrent_signal_assignment_statement.

• architecture_statement_part
• block_statement_part

Further definitions

Conditional_signal_assignment.

target <= options conditional_waveforms ;

selected_signal_assignment

with expression select target <= options selected_waveforms ;

Additional information

With a conditional signal assignment there is always an equivalent process statement; in general, this is valid for all concurrent assignments.

The equivalent process statement of a concurrent signal assignment statement including the keyword POSTPONED is a postponed process.

If the conditional signal assignment has the form

the signal assignment in the corresponding process statement has the form

If the (conditional) waveform is a simple waveform the signal assignment in the corresponding process statement has the form

The process statement of the wave_transform of a waveform of the form

has the form

null is here a null statement, not a null transaction!

The waveforms` characteristics and the conditions contained in the signal assignment have to be formulated appropriately so that the IF-statement in the corresponding process statement is a permitted statement.

With a selecting signal assignment there is always an equivalent process statement. If the selecting signal assignment has the form

For wave_transform look at the previous topic on conditional signal assignment.

The characteristics of the selected expression, of the waveforms and the criteria of selection contained in the signal assignment have to be formulated appropriately so that the CASE statement in the corresponding process statement is a permitted statement.

If the option GUARDED is contained in the signal assignment it is a so-called controlled assignment. If the target is also controlled the statement part of the corresponding process statement looks as follows:

If the target is not controlled the statement part of the corresponding process statement looks as follows:

It is also possible that neither signal assignment nor target is controlled. If this is the case the statement part of the corresponding process statement looks as follows:

It is not permitted to handle a signal assignment as being not controlled while handling the corresponding target as being controlled!

The value of b is assigned to the signal a after 5ns. In the first case the inertial delay model and in the second case the transport delay model is used.

The controlled signal assignment is only carried out if the corresponding condition in the block declaration is fulfilled.

If sel=0 then a is assigned the value 1 after 5ns; if sel=1 then a is assigned the value 0 after 3ns and the value 1 after 5ns; otherwise a is given the value X after 2 ns.

In this value assignment to the signal sig the value of of muxval is taken into consideration.

If muxval=0 then sig is assigned the value 001 etc. For this assignment the delay model TRANSPORT is used irrespective of the value of muxval .

S is only driven if the driver value is different the current value of S ; otherwise nothing happens.

Concurrent Signal Assignments :

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